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Serial Communications Interface Module (SCI)
Technical Data
254
Freescale Semiconductor, Inc.
With the misaligned character shown in
170 RT cycles at the point when the count of the transmitting device is
10 bit times × 16 RT cycles + 3 RT cycles = 163 RT cycles.
The maximum percent difference between the receiver count and the
transmitter count of a slow 9-bit character with no errors is
Fast Data Tolerance
Figure 18-8
shows how much a fast received character can be
misaligned without causing a noise error or a framing error. The fast stop
bit ends at RT10 instead of RT16 but is still there for the stop bit data
samples at RT8, RT9, and RT10.
RECEIVER
RT CLOCK
For an 8-bit character, data sampling of the stop bit takes the receiver
9 bit times × 16 RT cycles + 10 RT cycles = 154 RT cycles.
With the misaligned character shown in
154 RT cycles at the point when the count of the transmitting device is
10 bit times × 16 RT cycles = 160 RT cycles.
The maximum percent difference between the receiver count and the
transmitter count of a fast 8-bit character with no errors is
Serial Communications Interface Module (SCI)
For More Information On This Product,
Go to: www.freescale.com
Figure
–
170 163
×
100
=
4.12%
------------------------- -
170
STOP
DATA
SAMPLES
Figure 18-8. Fast Data
Figure
–
154 160
×
100
=
3.90%
------------------------- -
154
MC68HC908GP32
18-7, the receiver counts
IDLE OR NEXT CHARACTER
18-8, the receiver counts
·
MC68HC08GP32
Rev. 6
•
—
MOTOROLA
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