Timebase Register Description - Motorola MC68HC908GP32 Technical Data Manual

21.5 Timebase Register Description

MC68HC908GP32 MC68HC08GP32
•
MOTOROLA
Freescale Semiconductor, Inc.
The timebase has one register, the TBCR, which is used to enable the
timebase interrupts and set the rate.
Address: $001C
Bit 7 6
Read: TBIF
TBR2
Write:
Reset: 0 0
= Unimplemented
Figure 21-2. Timebase Control Register (TBCR)
TBIF — Timebase Interrupt Flag
This read-only flag bit is set when the timebase counter has rolled
over.
1 = Timebase interrupt pending
0 = Timebase interrupt not pending
TBR2:TBR0 — Timebase Rate Selection
These read/write bits are used to select the rate of timebase interrupts
as shown in Table
Table 21-1. Timebase Rate Selection for OSC1 = 32.768-kHz
TBR2 TBR1
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
Rev. 6
—
Timebase Module (TBM)
For More Information On This Product,
Go to: www.freescale.com
5 4 3
0
TBR1 TBR0
TACK
0 0 0
R
21-1.
TBR0 Divider
0 32768
1 8192
0 2048
1 128
0 64
1 32
0 16
1 8
Timebase Module (TBM)
Timebase Register Description
2 1 Bit 0
TBIE TBON
0 0
= Reserved
Timebase Interrupt Rate
Hz ms
1 1000
4 250
16 62.5
256 ~ 3.9
512 ~2
1024 ~1
2048 ~0.5
4096 ~0.24
Technical Data
R
0
337