Stop Mode - Motorola MC68HC908GP32 Technical Data Manual

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Low-Power Modes

3.4.2 Stop Mode

3.5 Central Processor Unit (CPU)
3.5.1 Wait Mode
3.5.2 Stop Mode
3.6 Clock Generator Module (CGM)
3.6.1 Wait Mode
Technical Data
60
Freescale Semiconductor, Inc.
The break module is inactive in stop mode. A break interrupt causes exit
from stop mode and sets the SBSW bit in the break status register. The
STOP instruction does not affect break module register states.
The WAIT instruction:
Clears the interrupt mask (I bit) in the condition code register,
enabling interrupts. After exit from wait mode by interrupt, the I bit
remains clear. After exit by reset, the I bit is set.
Disables the CPU clock
The STOP instruction:
Clears the interrupt mask (I bit) in the condition code register,
enabling external interrupts. After exit from stop mode by external
interrupt, the I bit remains clear. After exit by reset, the I bit is set.
Disables the CPU clock
After exiting stop mode, the CPU clock begins running after the oscillator
stabilization delay.
The CGM remains active in wait mode. Before entering wait mode,
software can disengage and turn off the PLL by clearing the BCS and
PLLON bits in the PLL control register (PCTL). Less power-sensitive
Low-Power Modes
For More Information On This Product,
Go to: www.freescale.com
MC68HC908GP32
MC68HC08GP32
Rev. 6
MOTOROLA

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