Flag Clearing Sequence - Motorola MC68HC908GP32 Technical Data Manual

BYTE 1
BYTE 1
MC68HC908GP32 MC68HC08GP32
•
MOTOROLA
Freescale Semiconductor, Inc.
NORMAL FLAG CLEARING SEQUENCE
BYTE 2
READ SCS1 READ SCS1
SCRF = 1
OR = 0
READ SCDR READ SCDR
BYTE 1
DELAYED FLAG CLEARING SEQUENCE
BYTE 2
READ SCS1
SCRF = 1
OR = 0
READ SCDR
BYTE 1
Figure 18-13. Flag Clearing Sequence
PE — Receiver Parity Error Bit
This clearable, read-only bit is set when the SCI detects a parity error
in incoming data. PE generates an SCI error CPU interrupt request if
the PEIE bit in SCC3 is also set. Clear the PE bit by reading SCS1
with PE set and then reading the SCDR. Reset clears the PE bit.
1 = Parity error detected
0 = No parity error detected
Rev. 6
—
Serial Communications Interface Module (SCI)
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Serial Communications Interface Module (SCI)
BYTE 3
READ SCS1
SCRF = 1 SCRF = 1
OR = 0
READ SCDR
BYTE 2
BYTE 3
READ SCS1
SCRF = 1
READ SCDR
I/O Registers
BYTE 4
OR = 0
BYTE 3
BYTE 4
OR = 1
BYTE 3
Technical Data
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