Tim Channel 0 Register High (Tch0H) - Motorola MC68HC908GP32 Technical Data Manual

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Timer Interface Module (TIM)
Technical Data
364
Freescale Semiconductor, Inc.
In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the
TIM channel x registers (TCHxH) inhibits input captures until the low
byte (TCHxL) is read.
In output compare mode (MSxB:MSxA ≠ 0:0), writing to the high byte of
the TIM channel x registers (TCHxH) inhibits output compares until the
low byte (TCHxL) is written.
Address: T1CH0H, $0026 and T2CH0H, $0031
Bit 7
6
Read:
Bit 15
14
Write:
Reset:
Figure 22-12. TIM Channel 0 Register High (TCH0H)
Address: T1CH0L, $0027 and T2CH0L $0032
Bit 7
6
Read:
Bit 7
6
Write:
Reset:
Figure 22-13. TIM Channel 0 Register Low (TCH0L)
Address: T1CH1H, $0029 and T2CH1H, $0034
Bit 7
6
Read:
Bit 15
14
Write:
Reset:
Figure 22-14. TIM Channel 1 Register High (TCH1H)
Address: T1CH1L, $002A and T2CH1L, $0035
Bit 7
6
Read:
Bit 7
6
Write:
Reset:
Figure 22-15. TIM Channel 1 Register Low (TCH1L)
Timer Interface Module (TIM)
For More Information On This Product,
Go to: www.freescale.com
5
4
3
13
12
11
Indeterminate after reset
5
4
3
5
4
3
Indeterminate after reset
5
4
3
13
12
11
Indeterminate after reset
5
4
3
5
4
3
Indeterminate after reset
MC68HC908GP32
2
1
Bit 0
10
9
Bit 8
2
1
Bit 0
2
1
Bit 0
2
1
Bit 0
10
9
Bit 8
2
1
Bit 0
2
1
Bit 0
MC68HC08GP32
Rev. 6
MOTOROLA

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