Sim Bus Clock Control And Generation; Bus Timing; Clock Startup From Por Or Lvi Reset - Motorola MC68HC908GP32 Technical Data Manual

19.3 SIM Bus Clock Control and Generation

OSC2
OSC1
OSCSTOPENB
FROM
CONFIG
CGMRCLK
PHASE-LOCKED LOOP (PLL)

19.3.1 Bus Timing

19.3.2 Clock Startup from POR or LVI Reset

MC68HC908GP32 MC68HC08GP32
•
MOTOROLA
Freescale Semiconductor, Inc.
The bus clock generator provides system clock signals for the CPU and
peripherals on the MCU. The system clocks are generated from an
incoming clock, CGMOUT, as shown in
come from either an external oscillator or from the on-chip PLL.
Section 7. Clock Generator Module
OSCILLATOR (OSC)
CGMXCLK
Figure 19-3. CGM Clock Signals
In user mode, the internal bus frequency is either the crystal oscillator
output (CGMXCLK) divided by four or the PLL output (CGMVCLK)
divided by four.
When the power-on reset module or the low-voltage inhibit module
generates a reset, the clocks to the CPU and peripherals are inactive
Rev. 6
—
System Integration Module (SIM)
For More Information On This Product,
Go to: www.freescale.com
SIM Bus Clock Control and Generation
Figure
(CGMC).)
TO TIMTB15A, ADC
SIM COUNTER
CGMOUT
÷ 2
SIMDIV2
System Integration Module (SIM)
19-3. This clock can
SIM
SIMOSCEN
IT12
TO REST
OF CHIP
BUS CLOCK
IT23
GENERATORS
TO REST
OF CHIP
PTC3
MONITOR MODE
USER MODE
Technical Data
(See
281