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3.0
Technical Reference
3.1
Memory Resources
Detailed memory information for addressable memory and memory maps can be found
in the Intel
3.2
DMA Channels
The DMA Channels below specify Partial DMA channels that are routed to specific
devices as well as other channels that are available.
Table 9.
DMA Channels
Data Channel
0
1
2
3
4
5
6
7
3.3
Fixed I/O Map
Refer to the Intel
3.4
Interrupts
Interrupts can be routed through the I/O xAPIC and supports a total of 24 interrupts.
The I/O xAPIC is supported by Microsoft Windows XP*.
the interrupts and there correlating functions.
Dual-Core Intel® Xeon® Processor LV and Intel
User's Manual
38
®
3100 Chipset External Design Specification.
Data Width
8
8
8
8
8 or 16 bits
16 bits
16 bits
16 bits
®
3100 Chipset External Design Specification for this information.
®
3100 Chipset
Technical Reference
System Resource
Open
Parallel Port
Diskette Drive
Parallel Port (for ECP or EPP)
DMA Controller
Open
Open
Open
Table 10 on page 39
Order Number:315879-002
provides
January 2007
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