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CLKOUT
NMI/INTx
ALE
S2:0
AD15:0
[AD7:0]
[A15:8]
A19:16
BHE
RFSH
NOTES: 1. For NMI, delay = 4 1/2 clocks. For INTx, delay = 7 1/2 clocks (min).
3.6
SYSTEM DESIGN ALTERNATIVES
Most system designs require no signals other than those already provided by the BIU. However,
heavily loaded bus conditions, slow memory or peripheral device performance and off-board de-
vice interfaces may not be supported directly without modifying the BIU interface. The following
sections deal with topics to enhance or modify the operation of the BIU.
Note 1
2. Previous bus cycle value.
Figure 3-29. Exiting HALT
BUS INTERFACE UNIT
Note 2
Note 2
Note 2
Note 2
Valid
Addr
Address
Addr
A1517-0A
3-33
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