Reload Counter - Fujitsu 8FX Hardware Manual

MB95630H Series
■ Block Diagram of LIN-UART
Machine
clock
Reload
counter
SCK
Pin
SIN
Restart receive
Pin

reload counter

Over-
sampling
circuit
Internal signal
to 8/16-bit
LIN break/
composite timer
SynField
detection
circuit
PE
ORE
FRE
RDRF
SSR
TDRE
register
BDS
RIE
TIE
● Reload counter
This block is a 15-bit reload counter functioning as a dedicated baud rate generator. The block
consists of a 15-bit register for reload values; it generates the transmit/receive clock from the
external or internal clock. The count value in the transmit reload counter is read from the baud
rate generator1, 0 (BGR1 and BGR0).
MN702-00009-2v0-E
Figure 14.2-1 Block Diagram of LIN-UART
OTO,
EXT,
REST
Transmit clock
Receive clock
Receive control
circuit
Start bit
detection
circuit
Receive
bit counter
Receive
parity counter
Receive
shift register
Error
detection
RDR
PE
ORE
FRE
Internal data bus
PEN
MD1
MD0 P
SBL
OTO
EXT SMR
CL
REST
register AD
CRE
UPCL
RXE
SCKE
SOE
TXE
FUJITSU SEMICONDUCTOR LIMITED
Transmit
control circuit
Transmit
start circuit
Transmit
bit counter
Transmit
parity counter
RDRF
SIN
Transmit
shift register
TDR
LBD
LBIE
LBD
LBL1
LBL0
SCR
ESCR
SOPE
register
register
SIOP
CCO
SCES
CHAPTER 14 LIN-UART
14.2 Configuration
PE ORE FRE
TIE
RIE
LBIE
Interrupt
LBD
generation
circuit
RBI
TBI
Receive
IRQ
Transmit
TDRE
IRQ
SOT
Pin
SOT
SIN
LIN break
generation
circuit
Start
transmis-
sion
Bus idle
LBR
detection
LBL1
circuit
LBL0
RBI TBI
LBR
MS
SCDE
ECCR
SSM
register
RBI
TBI
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