Signal Design Restrictions (Ddr3 Interface Part); Definition Of Signal Line Group - Fujitsu MB86R12 Design Manualline

MB86R12 Application Note
DDR3 Interface PCB Design Guideline
4.

Signal design restrictions (DDR3 interface part)

This chapter describes the signal wiring design restrictions for the DDR3 interface part.
4.1.

Definition of signal line group

In order to make the requirements for wiring configurations described further on in this document easier to
understand, the DDR3 interface signals are classified into the groups listed below.
Table 4-1 DDR3 interface signal grouping
Wiring
preferential Group name
order
1 MCK_Group
2 MDQS0_Group
MDQS1_Group
MDQS2_Group
MDQS3_Group
3 MDQ0_Group
MDQ1_Group
MDQ2_Group
MDQ3_Group
4 MCNTL_Group
5 MCMD_Group
FUJITSU SEMICONDUCTOR CONFIDENTIAL
MCK, MXCK
MDQS0, MXDQS0
MDQS1, MXDQS1
MDQS2, MXDQS2
MDQS3, MXDQS3
MDQ0~MDQ7, MDM0
MDQ8~MDQ15, MDM1
MDQ16~MDQ23, MDM2
MDQ24~MDQ31, MDM3
MCKE, MXCS, MODT
MA0~MA14, MBA0~MBA2, MXCAS, MXRAS, MXWE
4
Pin name of MB86R12