80C186Ec Peripheral Architecture; Interrupt Control Unit; Timer Counter Unit - Intel 80C186EB Manual

(A) Crystal Connection
NOTE
The L C network is only required when using a third-
1 1
overtone crystal
The following parameters are recommended when
choosing a crystal
Temperature Range
ESR (Equivalent Series Resistance)
C0 (Shunt Capacitance of Crystal)
C (Load Capacitance)
L
Drive Level
80C186EB PERIPHERAL
ARCHITECTURE
The 80C186EB has integrated several common sys-
tem peripherals with a CPU core to create a com-
pact yet powerful system The integrated peripher-
als are designed to be flexible and provide logical
interconnections between supporting units (e g the
interrupt control unit supports interrupt requests
from the timer counters or serial channels)
The list of integrated peripherals includes

7-Input Interrupt Control Unit

3-Channel Timer Counter Unit

2-Channel Serial Communications Unit

10-Output Chip-Select Unit

I O Port Unit

Refresh Control Unit
 Power Management Unit
The registers associated with each integrated peri-
heral are contained within a 128 x 16 register file
called the Peripheral Control Block (PCB) The PCB
can be located in either memory or I O space on
any 256 Byte address boundary
80C186EB 80C188EB 80L186EB 80L188EB
272433–3
Figure 2 Clock Configurations
Figure 3 provides a list of the registers associated
with the PCB The Register Bit Summary at the end
of this specification individually lists all of the regis-
Application Specific ters and identifies each of their programming attri-
40X max butes
7 0 pF max
20 pF 2 pF
g

Interrupt Control Unit

1 mW max
The 80C186EB can receive interrupts from a num-
ber of sources both internal and external The inter-
rupt control unit serves to merge these requests on
a priority basis for individual service by the CPU
Each interrupt source can be independently masked
by the Interrupt Control Unit (ICU) or all interrupts
can be globally masked by the CPU
Internal interrupt sources include the Timers and Se-
rial channel 0 External interrupt sources come from
the five input pins INT4 0 The NMI interrupt pin is
not controlled by the ICU and is passed directly to
the CPU Although the Timer and Serial channel
each have only one request input to the ICU sepa-
rate vector types are generated to service individual
interrupts within the Timer and Serial channel units

Timer Counter Unit

The 80C186EB Timer Counter Unit (TCU) provides
three 16-bit programmable timers Two of these are
highly flexible and are connected to external pins for
control or clocking A third timer is not connected to
any external pins and can only be clocked internally
However it can be used to clock the other two timer
channels The TCU can be used to count external
events time external events generate non-repeti-
tive waveforms generate timed interrupts etc
272433 – 4
(B) Clock Connection
5