Features; Power-On Configuration Options; Clock Control And Low Power States; Power-On Configuration Option Pins - Intel Xeon Datasheet

7.0

Features

7.1

Power-On Configuration Options

Several configuration options can be configured by hardware. The Intel® Xeon™ processor with
800 MHz system bus samples its hardware configuration at reset, on the active-to-inactive
transition of RESET#. For specifics on these options, please refer to
The sampled information configures the processor for subsequent operation. These configuration
options cannot be changed except by another reset. All resets reconfigure the processor, for reset
purposes, the processor does not distinguish between a "warm" reset and a "power-on" reset.
Table 28.

Power-On Configuration Option Pins

Output tri state
Execute BIST (Built-In Self Test)
In Order Queue de-pipelining (set IOQ depth to 1)
Disable MCERR# observation
Disable BINIT# observation
Disable bus parking
Symmetric agent arbitration ID
Disable Hyper-Threading Technology
NOTES:
1. Asserting this signal during RESET# will select the corresponding option.
2. Address pins not identified in this table as configuration options should not be asserted during RESET#.
3. The Intel® Xeon™ processor with 800 MHz system bus only uses the BR0# and BR1# signals. Platforms
must not use BR2# and BR3# signals.
7.2

Clock Control and Low Power States

The processor allows the use of HALT, Stop-Grant and Sleep states to reduce power consumption
by stopping the clock to internal sections of the processor, depending on each particular state. See
Figure 15
The state requires chipset and BIOS support on multiprocessor systems. In a multiprocessor
°
system, all the STPCLK# signals are bussed together, thus all processors are affected in unison.
The Hyper-Threading Technology feature adds the conditions that all logical processors share the
same STPCLK# signal internally. When the STPCLK# signal is asserted, the processor enters the
state, issuing a
needs to account for a variable number of processors asserting the
allowing the processor to be transitioned into one of the lower processor power states. Refer to the
applicable chipset specification for more information.
Due to the inability of processors to recognize bus transactions during the Sleep state,
multiprocessor systems are not allowed to simultaneously have one processor in Sleep state and the
other processors in Normal or Stop-Grant state.
Datasheet
Configuration Option
for a visual representation of the processor low power states.
Special Bus Cycle (SBC) for each processor or logical processor. The chipset
°
Intel® Xeon™ Processor with 800 MHz System Bus
Pin
SMI#
INIT#
A7#
A9#
A10#
A15#
BR[3:0]#
A31#
°
Table 15.
Notes
1,2
1,2
1,2
1,2
1,2
1,2
1,2,3
1,2
SBC on the bus before
°
75