Gtl+ Asynchronous And Agtl+ Asynchronous Signals; Signal Description Table; Signal Reference Voltages - Intel Xeon Datasheet

Intel® Xeon™ Processor with 800 MHz System Bus
Table 6 outlines the signals which include on-die termination (R
additional on-die resistance (R
reference voltages
Table 6.

Signal Description Table

A[35:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BINIT#,
BNR#, BOOT_SELECT
DBI[3:0]#, DBSY#, DEFER#, DP[3:0]#, DRDY#,
DSTBN[3:0]#, DSTBP[3:0]#, FORCEPR#, HIT#,
HITM#, LOCK#, MCERR#, OPTIMIZED/
COMPAT#
SLEW_CTRL, TEST_BUS, TRDY#
BINIT#, BNR#, HIT#, HITM#, MCERR#
Open Drain Signals
BPM[5:0]#, BR0#, BSEL[1:0], FERR#/PBE#, IERR#, TDO, THERMTRIP#, VID[5:0]
NOTES:
1. Signals that do not have R
2. The termination for these signals is not R
500 - 5000 Ω pull-up to V
Table 7.

Signal Reference Voltages

A20M#, A[35:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#,
BINIT#, BNR#, BPM[5:0]#, BPRI#, BR[3:0]#,
D[63:0]#, DBI[3:0]#, DBSY#, DEFER#, DP[3:0]#,
DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, FORCEPR#,
HIT#, HITM#, IGNNE#, INIT#, LINT0/INTR, LINT1/
NMI, LOCK#, MCERR#, ODTEN, RESET#,
REQ[4:0]#, RS[2:0]#, RSP#, SLEW_CTRL, SLP#,
SMI#, STPCLK#, TRDY#
NOTES:
1. These signals also have hysteresis added to the reference voltage. See
2.7

GTL+ Asynchronous and AGTL+ Asynchronous Signals

The Intel® Xeon™ processor with 800 MHz system bus does not use CMOS voltage levels on any
signals that connect to the processor silicon. As a result, input signals such as A20M#,
FORCEPR#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, SMI#, SLP#, and STPCLK# use GTL
20
). O.pen drain signals are also included.
L
Signals with R
TT
2
, BPRI#, D[63:0]#,
2
, REQ[4:0]#, RS[2:0]#, RSP#,
Signals with R
L
1
, nor are actively driven to their high voltage level.
TT
.
TT
GTLREF
TT
Signals with No R
A20M#, BCLK[1:0], BPM[5:0]#, BR[3:0]#, BSEL[1:0],
COMP[1:0], FERR#/PBE#, GTLREF[3:0], IERR#,
IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, ODTEN,
PROCHOT#, PWRGOOD, RESET#, SKTOCC#, SLP#,
SMI#, STPCLK#, TCK, TDI, TDO, TESTHI[6:0],
THERMDA, THERMDC, THERMTRIP#, TMS, TRST#,
VID[5:0], VIDPWRGD, VTTEN
Signals with No R
A20M#, A[35:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#,
BCLK[1:0], BPM[5:0]#, BPRI#, BR[3:0]#, BSEL[1:0],
2
BOOT_SELECT , COMP[1:0], D[63:0]#, DBI[3:0]#,
DBSY#, DEFER#, DP[3:0]#, DRDY#, DSTBN[3:0]#,
DSTBP[3:0]#, FERR#/PBE#, FORCEPR#,
GTLREF[3:0], IERR#, IGNNE#, INIT#, LINT0/INTR,
LINT1/NMI, LOCK#, ODTEN, OPTIMIZED/COMPAT#
PROCHOT#, PWRGOOD, REQ[4:0]#, RESET#,
RS[2:0]#, RSP#, SKTOCC#, SLEW_CTRL, SLP#, SMI#,
STPCLK#, TCK, TDI, TDO, TEST_BUS, TESTHI[6:0],
THERMDA, THERMDC, THERMTRIP#, TMS, TRDY#,
TRST#, VID[5:0], VIDPWRGD, VTTEN
. The OPTIMIZED/COMPAT# and BOOT_SELECT pins have a
TT
BOOT_SELECT, OPTIMIZED/COMPAT#, PWRGOOD
1 1 1
TCK , TDI , TMS , TRST#
) and lists signals which include
Table 7 provides signal
TT
L
0.5 * V
TT
1
, VIDPWRGD
Table 14 for more information.
Datasheet
2
,
1
,