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In the SET topology, the only termination is on the Intel
no termination present at the other end of the network. Due to the lack of termination, SET exhibits
much more ringback than the dual terminated topology. Extra care is required in SET simulations
to make sure that the ringback specs are met under the worst case signal quality conditions.
In addition, since there is only one pull-up resistor per net the rising edge response is substantially
degraded when using slow corner buffers. This effect manifests itself as a degraded flight time,
which results in a reduced maximum trace length that meets the 100 MHz timing requirements.
This loss of design flexibility must be carefully weighed against the cost savings from removing
the resistors.
Figure 2-10. Topology for Single Processor Designs With Single-End Termination (SET)
2.3.5.2
SET Trace Length Requirements
Intel has performed sensitivity analysis on the SET topology. The required trace lengths for
operation at 100 MHz with the SET topology are based on the sensitivity analysis results, and are
listed in
Table
that all traces used the microstrip propagation velocity range. The slower propagation of stripline
transmission line structures is not included in the recommendations of
Table 2-3. SET Trace Length Requirements
Trace
L1
Figure 2-11. Solution Space for Single Processor Designs With Single-End Termination (SET)
0.0
®
Intel
440GX AGPset Design Guide
2-3. Intel's SET simulations were performed assuming a four layer system board, so
Minimum Length
1.50"
1.0
2.0
3.0
L1 [in]
Motherboard Layout and Routing Guidelines
®
®
Pentium
II processor substrate. There is
Intel
440GX
L1
AGPset
Table
Maximum Length
4.00"
2.5
2.0
1.5
4.0
5.0
®
2-3.
SUBSTRATE
TRACE LENGTH
[IN]
2-9
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