A Programming Instructions - Omron CPM1 - PROGRAMING MANUAL 02-2001 Programming Manual

A PC instruction is input either by pressing the corresponding Programming Console key(s) (e.g., LD, AND, OR,
NOT) or by using function codes. To input an instruction with its function code, press FUN, the function code, and
then WRITE. Refer to the pages listed programming and instruction details.
Code Mnemonic
— AND AND
— AND LD AND LOAD
— AND NOT AND NOT
— CNT COUNTER
— LD LOAD
— LD NOT LOAD NOT
— OR OR
— OR LD OR LOAD
— OR NOT OR NOT
— OUT OUTPUT
— OUT NOT OUTPUT NOT
— RSET RESET
— SET SET
— TIM TIMER
00 NOP NO OPERATION
01 END END
02 IL INTERLOCK
03 ILC INTERLOCK CLEAR
04 JMP JUMP
05 JME JUMP END
06 (@)FAL FAILURE ALARM AND
RESET
07 FALS SEVERE FAILURE
ALARM
08 STEP STEP DEFINE
09 SNXT STEP START
10 SFT SHIFT REGISTER
11 KEEP KEEP
12 CNTR REVERSIBLE
COUNTER
13 DIFU DIFFERENTIATE UP
Appendix A
Programming Instructions
Name
Logically ANDs status of designated bit with execution condi-
tion.
Logically ANDs results of preceding blocks.
Logically ANDs inverse of designated bit with execution
condition.
A decrementing counter.
Used to start instruction line with the status of the designated
bit or to define a logic block for use with AND LD and OR LD.
Used to start instruction line with inverse of designated bit.
Logically ORs status of designated bit with execution condi-
tion.
Logically ORs results of preceding blocks.
Logically ORs inverse of designated bit with execution condi-
tion.
Turns ON operand bit for ON execution condition; turns OFF
operand bit for OFF execution condition.
Turns operand bit OFF for ON execution condition; turns op-
erand bit ON for OFF execution condition (i.e., inverts opera-
tion).
Turns the operand bit OFF when the execution condition is
ON, and does not affect the status of the operand bit when
the execution condition is OFF.
Turns the operand bit ON when the execution condition is
ON, and does not affect the status of the operand bit when
the execution condition is OFF.
ON-delay (decrementing) timer operation.
Nothing is executed and program moves to next instruction.
Required at the end of the program.
If interlock condition is OFF, all outputs are turned OFF and
all timer PVs reset between this IL(02) and the next ILC(03). all timer PVs reset between this IL(02) and the next ILC(03).
Other instructions are treated as NOP; counter PVs are
maintained.
If jump condition is OFF, all instructions between JMP(04) j p
and the corresponding JME(05) are ignored. d th
Generates a non-fatal error and outputs the designated FAL
number to the Programming Console.
Generates a fatal error and outputs the designated FALS
number to the Programming Console.
When used with a control bit, defines the start of a new step
and resets the previous step. When used without N, defines
the end of step execution.
Used with a control bit to indicate the end of the step, reset
the step, and start the next step.
Creates a bit shift register.
Defines a bit as a latch controlled by set and reset inputs.
Increases or decreases PV by one whenever the increment
input or decrement input signals, respectively, go from OFF
to ON.
Turns ON the designated bit for one cycle on the rising edge
of the input signal.
Function
,
di JME(05) i d
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