Omron CPM1 - PROGRAMING MANUAL 02-2001 Programming Manual page 368

Basic Ladder Diagrams
TR Bits
TR 0
00000
Diagram B: Corrected Using a TR bit
TR 0
00000
350
The TR area provides eight bits, TR 0 through TR 7, that can be used to tempo-
rarily preserve execution conditions. If a TR bit is placed at a branching point, the
current execution condition will be stored at the designated TR bit. When return-
ing to the branching point, the TR bit restores the execution status that was
saved when the branching point was first reached in program execution.
The previous diagram B can be written as shown below to ensure correct execu-
tion. In mnemonic code, the execution condition is stored at the branching point
using the TR bit as the operand of the OUTPUT instruction. This execution
condition is then restored after executing the right-hand instruction by using the
same TR bit as the operand of a LOAD instruction
00001
00002
In terms of actual instructions the above diagram would be as follows: The status
of IR 00000 is loaded (a LOAD instruction) to establish the initial execution
condition. This execution condition is then output using an OUTPUT instruction
to TR 0 to store the execution condition at the branching point. The execution
condition is then ANDed with the status of IR 00001 and instruction 1 is executed
accordingly. The execution condition that was stored at the branching point is
then re-loaded (a LOAD instruction with TR 0 as the operand), this is ANDed with
the status of IR 00002, and instruction 2 is executed accordingly.
The following example shows an application using two TR bits.
TR 1
00001 00002
00003
00004
00005
In this example, TR 0 and TR 1 are used to store the execution conditions at the
branching points. After executing instruction 1, the execution condition stored in
TR 1 is loaded for an AND with the status IR 00003. The execution condition
stored in TR 0 is loaded twice, the first time for an AND with the status of IR
00004 and the second time for an AND with the inverse of the status of IR 00005.
Address
00000
Instruction 1
00001
00002
Instruction 2
00003
00004
00005
00006
Address
00000
Instruction 1
00001
00002
Instruction 2
00003
00004
Instruction 3
00005
00006
Instruction 4
00007
00008
00009
00010
00011
00012
00013
00014
Section
Instruction Operands
LD
OUT TR
AND
Instruction 1
LD TR
AND
Instruction 2
Instruction Operands
LD 00000
OUT TR
AND 00001
OUT TR
AND 00002
Instruction 1
LD TR
AND 00003
Instruction 2
LD TR
AND 00004
Instruction 3
LD TR
AND NOT 00005
Instruction 4
6-3
00000
0
00001
0
00002
0
1
1
0
0