Ddr2 Dimm Ordering Overview; Four-Dimm Implementation - Intel Xeon LV User Manual

Product Description
1.3.2

DDR2 DIMM Ordering Overview

Figure 2
Figure 2.

Four-DIMM Implementation

Intel® 3100
Chipset
Note: Figure 2, "Four-DIMM Implementation" on page 13
routed to these DIMMS.
The platform requires DDR2-400 DIMMs to be populated in order, starting with the
DIMM furthest from Intel
page 13). In addition, dual-rank DIMMs must be populated farthest from Intel
Chipset when a combination of single-rank and dual-rank DIMMs are used. This
recommendation is based on the chip select and on-die termination signals routing
requirements of the DDR2-400 interface. Intel recommends that you check for correct
DIMM placement during BIOS initialization and that all designs follow the DIMM
ordering, clock enable routing, command clock routing, and chip select routing shown
in Figure 2 on page
BIOS code.
The two DIMMs that are provided with the development kit are 1Gb single-rank DIMMs.
If other memory is used follow the illustrations in
Figure 3
populate one dual-rank and two single-rank DIMMs.
two dual-rank DIMMs.
January 2007
Order Number: 315879-002
shows the DIMM ordering and location.
®
3100 Chipset in a "fill-farthest" approach (see
13. This addressing must be maintained to be compliant with the
shows how to populate four single-rank DIMMs.
Single-Rank DIMMs utilize all 4 DIMMs
Fill Fourth Fill Third
D D
I I
M M
M M
0 1
* signifies that the chipselect is also
Figure 3,
Figure 4
Figure 5
Dual-Core Intel® Xeon® Processor LV and Intel
Dual-Rank DIMMs
Fill Second Fill First
D D
I I
M M
M M
2 3
Figure 2 on
®
3100
Figure 4, and Figure 5.
shows how to
shows how to populate
®
3100 Chipset
User's Manual
13