Dram Rank Temperature Write Data; Channel & Dimm Index Decoding - Intel Xeon Processor E5-1600 Datasheet

2.5.2.6.3 DRAM Rank Temperature Write
This feature allows the PECI host to program into the processor, the temperature for all
the ranks within a DIMM up to a maximum of four ranks as shown in
DIMM index and Channel index are specified through the parameter field as shown in
Table 2-7. This write is relevant in platforms that do not have on-die or on-board
DIMM thermal sensors to provide memory temperature information or if the processor
does not have direct access to the DIMM thermal sensors. This temperature
information is used by the processor in conjunction with the activity-based DRAM
temperature estimations.
Table 2-7. Channel & DIMM Index Decoding
Index Encoding
Figure 2-13. DRAM Rank Temperature Write Data
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2.5.2.6.4 DIMM Temperature Read
This feature allows the PECI host to read the temperature of all the DIMMs within a
channel up to a maximum of three DIMMs. This read is not limited to platforms using a
particular memory temperature source or temperature estimation method. For
platforms using DRAM thermal estimation, the PCU will provide the estimated
temperatures. Otherwise, the data represents the latest DIMM temperature provided
by the TSOD or on-board DIMM sensor and requires that CLTT (closed loop throttling
mode) be enabled and OLTT (open loop throttling mode) be disabled. Refer to
for channel index encodings.
Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families
Datasheet Volume One
000
001
010
011
24 23
Rank# 3 Rank# 2
Absolute Temp Absolute Temp
(in Degrees C) (in Degrees C)
15
Reserved
Physical Channel#
0
1
2
3
16 15
Rank# 1
Absolute Temp
(in Degrees C)
Rank Temperature Data
6 5 3
DIMM Index
Parameter format
Figure 2-13. The
Physical DIMM#
0
1
2
Reserved
8 7 0
Rank# 0
Absolute Temp
(in Degrees C)
2 0
Channel Index
Table 2-7
41