ST STM32L4 5 Series Reference Manual page 1723

RM0351
Table 309. OTG_FS register map and reset values (continued)
Offset Register
. .
. .
. .
. .
OTG_
DOEPTSIZ5
0xBB0
Reset value
OTG_
PCGCCTL
0xE00
Reset value
1. This bit is reserved for STM32L475xx/476xx/486xx devices.
Refer to
boundary addresses.
PKTCNT
0 0 0 0 0 0 0 0
Section 2.2.2: Memory map and register boundary addresses
.
.
.
.
0 0 0 0 0 0 0 0
DocID024597 Rev 5
USB on-the-go full-speed (OTG_FS)
XFRSIZ
0 0 0 0 0 0 0 0 0
0 0
for the register
0 0 0 0 0 0
0 0 0 0
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