ST STM32L4 5 Series Reference Manual page 1823

RM0351
Date
27-Feb-2017
Table 327. Document revision history (continued)
Revision
Section 40.8.8: Interrupt and status register
(USART_ISR),
reset values
LPUART:
Updated
using LPUART
SPI:
Updated
Section 42.4.14: CRC
Rx CRC register
Tx CRC register (SPIx_TXCRCR)
SAI:
Updated
Section 43.3.8: SAI clock
Example of possible audio frequency sampling range
Added
BxCAN:
Updated
bxCAN register map and reset values
Added
5
Figure 502: Dual CAN block diagram
(continued)
OTG_FS:
Updated
USB_FS peripheral-only
OTG reset register
Section 47.15.13: OTG core ID register
Section 47.15.32: OTG device configuration register
(OTG_DCFG),
gating control register
OTG_FS register map and reset values
DEBUG SUPPORT:
Updated
assignment,
Section 48.16.4: Debug MCU APB1 freeze
register1(DBGMCU_APB1FZR1),
Debug MCU APB1 freeze register 2
(DBGMCU_APB1FZR2),
TRACE pin
assignment,
values
DEVICE ELECTRONIC SIGNATURE:
Updated
DocID024597 Rev 5
Changes
Table 240: USART register map and
Section 41.4.11: Wakeup from Stop mode
Section 42.4.7: Configuration of
calculation,
(SPIx_RXCRCR),
Figure 459: Functional block
generator,
Section 43.3.2: SAI pins and internal signals
Section 46.9.4: CAN filter
Section : Dual CAN peripheral
Section 47.5.1: ID line
connection,
(OTG_GRSTCTL),
Section 47.15.53: OTG power and clock
(OTG_PCGCCTL),
Section 48.4.2: Flexible SWJ-DP pin
Section 48.6.1: MCU device ID
Table 323: Synchronous
assignment, Table 324: Flexible TRACE pin
Table 326: DBG register map and reset
Section 49.3: Package data register
Revision history
SPI,
Section 42.6.6: SPI
Section 42.6.7: SPI
diagram,
Table 254:
registers, Table 299:
configuration,
detection, Figure 519:
Section 47.15.5:
(OTG_CID),
Table 309:
code,
Section 48.16.5:
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