Table 327. Document Revision History - ST STM32L4 5 Series Reference Manual

RM0351
50 Revision history
Date
28-May-2015
15-Oct-2015

Table 327. Document revision history

Revision
1 Initial release.
PWR
Updated
Updated
Updated
Updated
Updated
Updated
Updated
Updated
Renamed bit EIWF into EIWUL in
control register 3
GPIO
Updated OSPEEDy[1:0] definition in
GPIO port output speed register (GPIOx_OSPEEDR) (x
= A..I).
FMC
Updated
registers 1..4
Updated
registers 1..4
2
ADC
Updated
Updated
conversion (ADSTP,
Added formula in Bullet.
VREFBUF
Updated
DFSDM
Updated clock range in
operation
format operation.
LCD
Updated
TSC
Updated
AHB clock
Updated
TIM2/TIM3/TIM4/TIM5
Updated
DocID024597 Rev 5
Changes
Section 5.1: Power supplies.
Section : Entering low power
Table 25: Sleep.
Table 26: Low-power sleep.
Table 27: Stop 0 mode.
Table 29: Stop 2 mode.
Table 30: Standby mode.
Table 27: Stop 0 mode.
(PWR_CR3).
Section : SRAM/NOR-Flash chip-select timing
(FMC_BTR1..4).
Section : SRAM/NOR-Flash write timing
(FMC_BWTR1..4).
Figure 69: ADC3 connectivity.
Section 18.3.17: Stopping an ongoing
JADSTP).
Table 138: VREFBUF buffer
Section : SPI data input format
and Section : Manchester coded data input
Section 25.2: LCD main
Table 167: Spread spectrum deviation versus
frequency.
Table 169: Effect of low-power modes on
Bullet in Section 31.3.13: One-pulse
Revision history
mode.
Section 5.4.3: Power
Section 8.4.3:
modes.
features.
TSC.
mode.
1811/1830
1823