ST STM32L4 5 Series Reference Manual page 1818

Revision history
Date
03-Jun-2016
27-Feb-2017
1818/1830
Table 327. Document revision history (continued)
Revision
SAI:
Replaced FLTH by FLVL in entire
audio interface
SWPMI:
Updated
activation.
USB:
Updated
Added
Updated
Updated
Updated
4
Updated
(continued)
Updated
registers
Updated
status
Updated
register
Updated
(OTG_GRSTCTL).
Updated
register
Updated
Updated
Update of the document to include support for
STM32L4x5, STM32L496xx and STM32L4A6xx.
SYSTEM AND MEMORY OVERVIEW:
Updated
Section 2.1.3: S2:
bus,
SRAM,
Boot configuration for STM32L475xx/476xx/486xx
devices
Added
5
STM32L496xx/4A6xx
DMA2D-bus,
STM32L496xx/4A6xx
STM32L496xx/4A6xx devices memory map and
peripheral register boundary
Boot configuration for STM32L496xx/4A6xx devices
FLASH:
Updated
CPU clock (HCLK)
programming,
Section 3.7.8: Flash option register (FLASH_OPTR)
DocID024597 Rev 5
Changes
(SAI).
Section 44.3.2: SWP initialization and
Section 47.1: Introduction.
Table 292: OTG_FS speeds
Section 47.8.1: Host
Section 47.8.2: Peripheral
Section 47.9: Power
Section 47.11.3: FIFO RAM
Table 294: Core global control and status
(CSRs).
Table 298: Power and clock gating control and
registers.
Section 47.15.1: OTG control and status
(OTG_GOTGCTL).
Section 47.15.5: OTG reset register
Section 47.15.32: OTG device configuration
(OTG_DCFG).
Section 47.16.3: Device
Section 47.16.5: Device programming
Section 2.1: System
S-bus, Section 2.1.4: S3, S4: DMA-
Section 2.1.6: BusMatrix,
Table 3: SRAM2 organization,
Figure 2: System architecture for
devices,
Figure 4: Memory map for
devices,
Table 11: Number of wait states according to
frequency,
Section 3.4.1: Option bytes
RM0351
Section 43: Serial
supported.
SOFs.
SOFs.
options.
allocation.
initialization.
model.
architecture,
Section 2.4: Embedded
Section 2.6.1:
Section 2.1.5: S5:
Table 2:
addresses, Section 2.6.2:
Section : Fast
description,