ST STM32L4 5 Series Reference Manual page 1812

Revision history
Date
15-Oct-2015
08-Dec-2015
1812/1830
Table 327. Document revision history (continued)
Revision
I2C
Updated
Figure 374: Setup and hold
Updated
(I2C_TIMINGR).
SPI
Updated
Figure
Notes updated and added below
Figure
2
Added
(continued)
UART
Updated Note:.
Added
baudrate allowing to wakeup correctly from Stop mode
when the USART clock source is the HSI
Removed TXFRQ bit in
map and reset
DEBUG
Updated
In all the document:
– Stop 1 with main regulator becomes Stop 0
– Stop 1 with low-power regulator remains as Stop 1
MEM
Updated SAI1 and SAI2 base address in
devices memory map and peripheral register boundary
addresses.
MMAP
Added
mode/physical
FLASH
Added
3
PWR
Updated
working
RCC
Updated WWDGEN bit description and access mode in
Section 6.4.19: APB1 peripheral clock enable register 1
(RCC_APB1ENR1).
NVIC
Updated
mapping.
Updated reset value in
register 2
DocID024597 Rev 5
Changes
Section 39.4.4: I2C initialization, including
timings.
Section 39.7.5: Timing register
Figure 441, Figure 442,
444.
442, Figure 443.
Section 42.4.4: Multi-master
Section : Determining the maximum USART
Table 241: LPUART register
values.
Section : DBGMCU_IDCODE.
Table 6: Memory mapping versus boot
remap.
Note: in Section : Fast programming.
Table 24: Functionalities depending on the
mode.
Figure 33: External interrupt/event GPIO
Section 14.5.7: Interrupt mask
(EXTI_IMR2).
RM0351
Figure 443 and
Figure 441,
communication.
clock.
Table 2: Cat. 2