ST STM32L4 5 Series Reference Manual page 1821

RM0351
Date
27-Feb-2017
Table 327. Document revision history (continued)
Revision
Table 83: FMC_BCRx bit
bit
FMC_BCRx bit
controller registers
QUADSPI:
Updated
QUADSPI main
signal interface protocol
QUADSPI memory-mapped
QUADSPI control register
QUADSPI register map and reset values
Added
Figure 59: QUADSPI block diagram when dual-flash
mode is
Section 17.4.5: QUADSPI indirect mode
ADC:
Updated
ADC block
Section 18.4.3:
programmable sampling time (SMPR1,
Table 107: ADC1, ADC2 and ADC3 - External triggers
for regular
ADC3 - External trigger for injected
Example of JSQR queue of context (sequence
5
Figure 81: Example of JSQR queue of context (trigger
(continued)
change),
with empty queue (case
JSQR queue of context by setting JADSTP=1 (JQM=0).
Case when JADSTP occurs during an ongoing
conversion. Section 18.4.26: Data
Section 18.6.4: ADC configuration register
(ADC_CFGR),
register 1
control register (ADC_CCR)
Added
Section 18.4.27: Managing conversions using the
DFSDM,
interleaved
simultaneous mode
DAC:
Updated
DAC block
right aligned data holding register (DAC_DHR8RD)
Added
DCMI: Added
(DCMI)
DFSDM:
Updated
internal
DocID024597 Rev 5
Changes
fields,
fields, Table 88: FMC_BCRx bit
fields, Section 16.5.6: NOR/PSRAM
Section 17.1: Introduction,
features, Section 17.4.4: QUADSPI
modes,
(QUADSPI_CR),
Section 17.3: QUADSPI
enabled, Section 17.4.2: QUADSPI
Section 18.2: ADC main
diagram, Table 104: ADC
Clocks, Section 18.4.12: Channel-wise
channels, Table 108: ADC1, ADC2 and
Figure 84: Example of JSQR queue of context
JQM=0),
Section 18.6.6: ADC sample time
(ADC_SMPR1), Section 18.7.2: ADC common
Section 18.3: ADC implementation,
Section : DFSDM mode in dual ADC
mode, Section : DFSDM mode in dual ADC
Section 19.1: Introduction,
diagram, Section 19.5.11: DUAL DAC 8-bit
Table 122: DAC trigger selection
Section 20: Digital camera interface
Section 24.1: Introduction,
signals, Table 154: DFSDM triggers connection
Revision history
Table 86: FMC_BCRx
fields, Table 90:
Section 17.2:
Section 17.4.7:
mode, Section 17.6.1:
Table 101:
implementation,
pins,
features, Figure 66:
pins,
SMPR2),
channels, Figure 80:
change),
Figure 86: Flushing
management,
Section 19.3.1:
Table 153: DFSDM
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