Pci Bus Overview; Table 9.2-2 - Data Acquisition Commands - Newport ESP6000 User Manual

Command
esp_set_adc_gain*
esp_get_adc_gain
esp_set_adc_range*
esp_get_adc_range
esp_get_adc*
esp_get_all_adc*
esp_set_daq_mode
esp_enable_daq
esp_get_daq_status
esp_daq_done
esp_get_daq_data
esp_disable_daq
* = Immediate execution-type
command, does not require
setup before execution
9.3

PCI Bus Overview

9 - 4
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Data acquisition commands are listed in Table 9.2-2 (refer to Section 5,
Commands, for additional details):
Table 9.2-2 — Data Acquisition Commands
Description
Sets gain
Sets polarity (uni-polar or bi-polar)
Selects channels, samples (one or more channels, one or more samples
for each channel)
Selects all eight channels at once
Sets the following:
(1) channel: select x channels of eight
(2) mode: immediate execution, when an axis begins movement, or
when an axis reaches a specific velocity
(3) number: number of samples, expressed as integer value
(4) position on axis: designates axis to be reported on
(5) timing: sets frequency/how often sampling is to occur
(6) trigger on axis: sets axis to be triggered on
Enables data acquisition
Returns the number of samples collected (but not the samples them-
selves) at the point in time the information is requested
Provides completion status for the number of samples requested
(0 = DAC armed/ready but not triggered, 1 = finished, -1 = acquiring)
Returns an array as specified
Disables data acquisition
Newport Corporation's ESP system employs the Compact Peripheral
Interconnect Component (PCI) bus for its high-performance motion
control and data acquisition applications. The ESP PCI bus structure is
described in the following paragraphs.
The PCI bus was designed for population with adapters requiring fast
accesses to each other and/or system memory and that can be accessed
by the host processor at speeds approaching that of the processor's full
native bus speed. All read and write transfers over the PCI bus are burst
transfers. The length of the burst is negotiated between the initiator and
target devices and may be of any length. Table 9.3-1 lists some of the
major PCI design goals.