Table 9.3-1 - Pci Design Goals - Newport ESP6000 User Manual

Feature
Address spaces
Auto configuration
Burst read and write transfers
Bus master support
Bus speed
Bus width
Concurrent bus operation
Expansion card definition
Expansion card size
Fast access
Hidden bus arbitration
Low pin-count
Low power consumption
Number of PCI buses supported The specification provides support for up to 256 PCI buses.
PCI functional devices
Processor independence
Software transparency
Transaction integrity check
Section 9 — Advanced Capabilities
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Table 9.3-1 — PCI Design Goals
Description
Full definition of three address spaces: memory, I/O, and configuration.
Full bit-level specification of the configuration registers necessary to
support automatic peripheral detection and configuration.
Burst mode for all read and write transfers. Supports 132 Mbytes-per-
second peak transfer rate for both read and write transfers.
Full support of PCI bus initiators allows peer-to-peer PCI bus access, as
well as access to main memory and expansion bus devices through PCI
and expansion bus bridges. In addition, a PCI master can access a
target that resides on another PCI bus lower in the bus hierarchy.
Revision 2.0 specification supports PCI bus speeds up to 33 MHz.
Full definition of a 64-bit extension.
High-end bridges support full bus concurrency with host bus, PCI bus,
and the expansion bus simultaneously in use.
The specification includes a definition of PCI connectors and add-in
cards.
The specification defines three card sizes: long, short, and variable-
height cards.
As fast as 60ns (at a bus speed of 33 MHz when an initiator parked on
the PCI bus is writing to a PCI target.
Arbitration for the PCI bus can take place while another bus master is in
possession of the PCI bus. This eliminates latency encountered during
bus arbitration on buses other than PCI.
Economical use of bus signals allows implementation of a functional PCI
target with 47 pins and a functional PCI bus initiator with 49 pins.
A major design goal of the PCI specification is the creation of a system
design that draws as little current a possible.
Although a typical PCI bus implementation supports approximately ten
supported electrical loads, each PCI device package may contain up to
eight separate PCI functions. The PCI bus logically supports up to 32
physical PCI device packages, for a total of 256 possible PCI functions
per PCI bus.
Components designed for the PCI bus are PCI-specific, not processor-
specific, thereby isolating device design from processor-upgrade
treadmill.
Software drivers utilize same command set and status definition when
communicating with PCI device or its expansion bus-oriented cousin.
Parity checking on the address, command, and data.
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