IDEC MICROSmart FC6A Series Ladder Programming Manual page 587

Instruction
RNDM
ANDW, ORW, XORW (W)
ANDW, ORW, XORW (D)
SFTL, SFTR
BCDLS
WSFT
ROTL, ROTR (W)
HTOB (W)
BTOH (W)
HTOA (W)
ATOH (W)
BTOA (W)
ATOB (W)
ENCO (W)
DECO
BCNT
ALT
CVDT
DTDV
DTCB
SWAP (W)
SWAP (D)
WKTIM
WKTBL
WEEK
YEAR
MSG
DISP
DGRD
LABEL
LJMP
LCAL
LRET
DJNZ
IOREF
HSCRF
FRQRF
COMRF
DI
EI
XYFS
CVXTY
CVYTX
AVRG (W, I)
AVRG (D, L)
AVRG (F)
PULS
PWM
RAMP
RAMPL
Device and Condition
D, D→D
M · M→D
D · D→D
D · D→D
N_B=100
D→D, S1=1
D→D
D, bits=1
D→D
D→D
D→D
D→D
D→D
D→D
M→D, bits=16
D→M
M→D, bits=16
―
W, I→F
D, L→F
F→W, I
F→D, L
D→D
D→D
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S3=10
S3=10
S3=10
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FC6A S MICROS L
ERIES MART
All-in-One CPU Module/
CAN J1939 All-in-One CPU
Module
6.84
6.08
6.2
21.6
14.10
10.36
15.6 + 1.4n
9.1
4.94
4.94
7.20
5.48 + 0.88n
5.88 + 0.72n
5.84 + 0.76n
3.9 + 0.8n
9.6
―
8.00
10.2
15.3
10.3
15.5
4.78
4.96
4.46
14.9
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9.48
8.32
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7.44
2.07
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―
7.76
13.5
14.4
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―
P M
ADDER ROGRAMMING ANUAL
Execution Time (μs)
Plus CPU Module
7.8 + 0.7n
2.74 + 0.44n
2.94 + 0.36n
2.92 + 0.38n
1.95 + 0.4n
FC9Y-B1726
A
PPENDIX
3.42
3.04
3.1
10.8
7.05
5.18
4.6
2.47
2.47
3.6
4.8
―
4.00
5.1
7.7
5.2
7.3
2.39
2.48
2.23
7.5
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4.74
4.16
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3.72
1.04
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3.88
6.8
7.2
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A-3