IDEC MICROSmart FC6A Series Ladder Programming Manual page 586

A
PPENDIX
Instruction
IMOV, IMOVN (D)
IMOV (F)
MOVC
BMOV
IBMV, IBMVN
NSET (W, I)
NSET (D, L)
NSET (F)
NRS (W, I)
NRS (D, L)
NRS (F)
XCHG (W)
XCHG (D)
TCCST (W)
TCCST (D)
CMP (=, <>, <, >, <=, >=) (W, I)
CMP (=, <>, <, >, <=, >=) (D, L)
CMP (=, <>, <, >, <=, >=) (F)
ICMP (>=)
ICMP (D, L, F)
< >
LC (=, <>, , , <=, >=) (W, I)
< >
LC (=, <>, , , <=, >=) (D, L)
< >
LC (=, <>, , , <=, >=) (F)
ADD (W, I)
ADD (D, L)
ADD (F)
SUB (W, I)
SUB (D, L)
SUB (F)
MUL (W, I)
MUL (D, L)
MUL (F)
DIV (W, I)
DIV (D, L)
DIV (F)
INC (W, I)
INC (D, L)
DEC (W, I)
DEC (D, L)
ROOT (W)
ROOT (D)
ROOT (F)
SUM (W, I)
SUM (D, L)
SUM (F)
A-2
Device and Condition
D+D→D+D
―
―
D→D
M+D→M+D
D+D→D+D
D→D
D→D
D→D
D, D→D
D, D→D
D, D→D
D⇔D
D⇔D
D→T
D→T
D⇔D→M
D⇔D→M
D⇔D→M
D⇔D⇔D→M
D⇔D⇔D→M
D⇔D
D⇔D
D⇔D
M+M→D
D+D→D
M+M→D
D+D→D
D+D→D
M-M→D
D-D→D
M-M→D
D-D→D
D-D→D
M×M→D
D×D→D
M×M→D
D×D→D
D×D→D
M÷M→D
D÷D→D
M÷M→D
D÷D→D
D÷D→D
―
―
―
―
D →D
D →D
D →D
D, D→D
D, D→D
D, D→D
FC6A S MICROS L
ERIES MART
All-in-One CPU Module/
CAN J1939 All-in-One CPU
Module
18.8
13.9
―
16.1 + 1.2n
13.4
13.4
2.28 + 2.2n
2.2 + 12.6n
2.2 + 12.6n
5.84 + 0.64n
11.1 + 5.7n
11.0 + 5.8n
5.32
26.0
4.68
15.0
27.6
38.0
38.2
29.0
44.6
4.84
15.2
15.3
11.6
11.7
27.2
27.2
27.8
11.6
11.7
27.2
27.2
27.4
11.2
11.3
27.2
27.2
27.4
7.0
6.96
28.0
28.0
28.0
8.92
19.3
8.92
19.2
6.24
18.0
19.4
11.3 + 0.8n
16.6 + 6.0n
16.8 + 7.0n
P M
ADDER ROGRAMMING ANUAL
Execution Time (μs)
Plus CPU Module
8.1 + 0.6n
1.14 +1.1n
1.1 + 6.3n
1.1 + 6.3n
2.92 + 0.32n
5.6 + 2.9n
5.5 + 2.9n
5.7 + 0.4n
8.3 + 3.0n
8.4 + 3.5n
FC9Y-B1726
9.4
7.00
―
6.7
6.7
2.66
13.0
2.34
7.5
13.8
19.0
19.1
14.5
22.3
2.42
7.6
7.7
5.8
5.9
13.6
13.6
13.9
5.8
5.9
13.6
13.6
13.7
5.6
5.7
13.6
13.6
13.7
3.5
3.48
14.0
14.0
14.0
4.46
9.65
4.46
9.6
3.12
9.0
9.7