IDEC MICROSmart FC6A Series Ladder Programming Manual page 351

ARAMP1 instruction (single-pulse output reversible control enabled) timing chart
ARAMP1 instruction, S1 is specified as data register D0200, S2 is specified as internal relay M0000, S3 is disabled, D1 is
specified as data register D0000, D2 is specified as internal relay M0050
ARAMP
1
ARAMP instruction
input
ARAMP instruction input
Control direction
Pulse frequency
Reversible control Q2 (All-in-One CPU module)
signal
Q1 (CAN J1939 All-in-One CPU module)
Pulse output ON
Pulse output complete
Pulse output status
When the ARAMP instruction input changes from off to on, pulses are output from Q0 according to the settings configured by the
data registers. The reversible control signal is output from Q2 or Q1. When pulse output starts, M0050 turns on. M0052 turns on
while the pulse frequency is increasing or decreasing. When the number of pulses configured for each step is output, the next step
is executed. When pulse output is complete for the step where the next step number is set to 0, then the pulses will stop. In this
situation, M0050 turns off and M0051 turns on.
If the ARAMP instruction input turns off during pulse output, pulse output ends. If this input turns on again, the operation starts
from the beginning. Even if the contents of the data registers are changed during pulse output, the change is not reflected in the
pulse output operation. The changed content is reflected the next time the ARAMP instruction is started.
In this application, switching between forward and reverse must be executed when the pulse frequency is decreased to the
minimum value, so a step is inserted to decrease the frequency before reversing.
S1 S2 S3 D1
D0200 M0000 D0000
0 (Forward)
Q0
M0050
M0051
M0052
FC6A S MICROS
ERIES MART
D2
M0050
L P M
ADDER ROGRAMMING ANUAL
18: P O
ULSE UTPUT
1 (Reverse)
FC9Y-B1726
I
NSTRUCTIONS
18-55