IDEC MICROSmart FC6A Series Ladder Programming Manual page 352

18: P O I
ULSE UTPUT NSTRUCTIONS
ARAMP1 instruction (dual-pulse output reversible control enabled) timing chart
All-in-One CPU module, ARAMP1 instruction, S1 is specified as data register D0200, S2 is specified as internal relay
M0000, S3 is disabled, D1 is specified as data register D0000, D2 is specified as internal relay M0050
ARAMP
1
ARAMP instruction
input
ARAMP instruction input
Forward pulse (CW) Q0
Reverse pulse (CCW) Q1
Control direction
Pulse output ON M0050
Pulse output
M0051
complete
Pulse output status M0052
When the ARAMP instruction input changes from off to on, pulses are output from Q0 according to the settings configured by the
data registers. The reversible control signal is output from Q0 or Q1. When pulse output starts, M0050 turns on. M0052 turns on
while the pulse frequency is increasing or decreasing. The pulses increase and decrease according to the frequency change time
until they reach the steady pulse frequency from the current pulse frequency. When the configured number of pulses are output,
the pulses stop. In this situation, M0050 turns off and M0051 turns on.
If the ARAMP instruction input turns off during pulse output, pulse output ends. If the ARAMP instruction input turns on again, the
operation starts from the beginning. Even if the contents of the data registers are changed during pulse output, the change is not
reflected in the pulse output operation. The changed content is reflected the next time the ARAMP instruction is started.
In this application, switching between forward and reverse must be executed when the pulse frequency is decreased to the
minimum value, so a step is inserted to decrease the frequency before reversing.
18-56
S1 S2 S3 D1
D0200 M0000 D0000
0 (Forward)
FC6A S MICROS L
ERIES MART
D2
M0050
1 (Reverse)
P M
ADDER ROGRAMMING ANUAL
FC9Y-B1726