Mitsubishi Electric Q172CPU Programming Manual page 84

3 COMMUNICATION BETWEEN THE PLC CPU AND THE MOTION CPU IN
THE MULTIPLE CPU SYSTEM
Shared CPU memory
of other CPU
CPU No.2
CPU No.2
transmitting data (No.1)
CPU No.2
transmitting data (No.2)
Maximum
2k words
CPU No.2
transmitting data (No.3)
CPU No.2
transmitting data (No.4)
CPU No.3
CPU No.3
transmitting data (No.1)
CPU No.3
transmitting data (No.2)
Maximum
2k words
CPU No.3
transmitting data (No.3)
CPU No.3
transmitting data (No.4)
CPU No.4
CPU No.4
transmitting data (No.1)
CPU No.4
transmitting data (No.2)
Maximum
2k words
CPU No.4
transmitting data (No.3)
CPU No.4
transmitting data (No.4)
3) The block diagram below illustrates the automatic refresh operation over
four ranges of setting 1: link relay (B), setting 2: link register (W), setting
3: data register (D), and setting 4: internal relay (M).
Device
Setting 1
B0
transmitting data
to
Read via END processing
of CPU No.1
receiving data (No.1)
receiving data (No.1)
receiving data (No.1)
Setting 2
W0
receiving data (No.2)
receiving data (No.2)
receiving data (No.2)
Setting 3
D0
receiving data (No.3)
receiving data (No.3)
receiving data (No.3)
Setting 4
M0
M0
receiving data (No.4)
receiving data (No.4)
receiving data (No.4)
3 - 7
CPU No.1
CPU No.1
Write during END processing
(No.1)
CPU No.2
CPU No.3
CPU No.4
CPU No.1
transmitting data
(No.2)
CPU No.2
CPU No.3
CPU No.4
Maximum
8k words
CPU No.1
transmitting data
(No.3)
CPU No.2
CPU No.3
CPU No.4
CPU No.1
transmitting data
(No.4)
CPU No.2
CPU No.3
CPU No.4
Shared CPU memory
CPU No.1
transmitting data
(No.1)
CPU No.1
transmitting data
(No.2)
CPU No.1
Maximum
transmitting data
2k words
(No.3)
CPU No.1
transmitting data
(No.4)
User-defined area