Table 8-5: Fpframe Polarity Selection; Vancouver Design Center - Epson S1D13504 Technical Manual

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Vancouver Design Center

VRTC/FPFRAME Pulse Width Register
REG[0Ch]
FPFRAME
VRTC Polarity
Polarity
Select
Select
bit 7
bit 6
FPFRAME Polarity Select
bits 2-0
Hardware Functional Specification
Issue Date: 01/11/06
n/a n/a
VRTC Polarity Select
For CRTs, this bit selects the polarity of the VRTC. When this bit = 1, the VRTC pulse is active
high. When this bit = 0, the VRTC pulse is active low.
FPFRAME Polarity Select
This bit selects the polarity of the FPFRAME for TFT and passive LCD. When this bit = 1, the
FPFRAME pulse is active high for TFT and active low for passive LCD. When this bit = 0, the
FRAME pulse is active low for TFT and active high for passive LCD.

Table 8-5: FPFRAME Polarity Selection

Passive LCD FPFRAME
0
1
VRTC/FPFRAME Pulse Width Bits [2:0]
For CRTs and TFTs, these bits specify the pulse width of VRTC and FPFRAME respectively. For
passive LCDs, FPFRAME is automatically created and these bits have no effect.
VRTC/FPFRAME pulse width (lines) = VRTC/FPFRAME Pulse Width Bits [2:0] + 1.
The maximum VRTC pulse width is 8 lines.
Note
This register must be programmed such that
(REG[0Ah] bits [5:0] + 1) ≥ (REG[0Bh] + 1) + (REG[0Ch] bits [2:0] + 1)
VRTC/
FPFRAME
n/a
Pulse Width
Bit 2
Polarity
active high
active low
VRTC/ VRTC/
FPFRAME FPFRAME
Pulse Width Pulse Width
Bit 1 Bit 0
TFT FPFRAME Polarity
active low
active high
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S1D13504
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