Table 7-21: Single Color 4-Bit Panel A.c. Timing; Figure 7-24: Single Color 4-Bit Panel A.c. Timing; Vancouver Design Center - Epson S1D13504 Technical Manual

Epson Research and Development

Vancouver Design Center

Sync Timing
Data Timing
Symbol
t1
FPFRAME setup to FPLINE falling edge
t2
FPFRAME hold from FPLINE falling edge
t3
FPLINE pulse width
t4
FPLINE period
t5
MOD transition to FPLINE falling edge
t6
FPSHIFT falling edge to FPLINE rising edge
t7
FPLINE falling edge to FPSHIFT falling edge
t8
FPSHIFT period
t9
FPSHIFT falling edge to FPLINE falling edge
t10
FPLINE falling edge to FPSHIFT rising edge
t11
FPSHIFT pulse width high
t12
FPSHIFT pulse width low
t13
UD[3:0], setup to FPSHIFT falling edge
t14
UD[3:0], hold from FPSHIFT falling edge
1. Ts = pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4 (see REG[19h] bits [1:0])
2. t1 = t4 - 9Ts
min min
3. t4 = [((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0]) + 1)*8] + 33 Ts
min
4. t5 = [((REG[04h] bits [6:0])+1)*8 - 1] Ts
min
5. t6 = [((REG[05h] bits [4:0]) + 1)*8 - 26] Ts
min
6. t9 = [((REG[05h] bits [4:0]) + 1)*8 - 17] Ts
min
Hardware Functional Specification
Issue Date: 01/11/06
FPFRAME
FPLINE
MOD
FPLINE
FPSHIFT
UD[3:0]

Figure 7-24: Single Color 4-Bit Panel A.C. Timing

Table 7-21: Single Color 4-Bit Panel A.C. Timing

Parameter
t1
t2
t3
t5
t6
t7
t9 t10
t13
t14 + 0.5
t4
t8
t11 t12
t14
1 2
Min Typ Max
note 2
9
9
note 3
33 note 4
note 5
1
note 6
19
0.45
0.45
0.45
0.45
Page 69
Units
Ts (note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
S1D13504
X19A-A-002-19