Table 8-4: Fpline Polarity Selection; Vancouver Design Center - Epson S1D13504 Technical Manual

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HRTC/FPLINE Pulse Width Register
REG[07h]
HRTC FPLINE
Polarity Polarity
Select Select
bit 7
bit 6
FPLINE Polarity Select
bits 3-0
Vertical Display Height Register 0
REG[08h]
Vertical Vertical
Display Display
Height Bit 7 Height Bit 6
Vertical Display Height Register 1
REG[09h]
n/a n/a
REG[08h] bits 7-0
REG[09h] bits 1-0
Hardware Functional Specification
Issue Date: 01/11/06
n/a n/a
HRTC Polarity Select
For CRTs, this bit selects the polarity of the HRTC. When this bit = 1, the HRTC pulse is active
high. When this bit = 0, the HRTC pulse is active low.
FPLINE Polarity Select
This bit selects the polarity of the FPLINE for TFT and passive LCD. When this bit = 1, the
FPLINE pulse is active high for TFT and active low for passive LCD. When this bit = 0, the
FPLINE pulse is active low for TFT and active high for passive LCD.

Table 8-4: FPLINE Polarity Selection

Passive LCD FPLINE Polarity
0
1
HRTC/FPLINE Pulse Width Bits [3:0]
For CRTs and TFTs, these bits specify the pulse width of HRTC and FPLINE respectively. For pas-
sive LCDs, FPLINE is automatically created and these bits have no effect.
HRTC/FPLINE pulse width (pixels) = (HRTC/FPLINE Pulse Width Bits [3:0] + 1) × 8.
The maximum HRTC pulse width is 128 pixels.
Note
This register must be programmed such that
(REG[05h] + 1) ≥ (REG[06h] + 1) + (REG[07h] bits [3:0] + 1)
Vertical Vertical
Display Display
Height Bit 5 Height Bit 4
n/a n/a
Vertical Display Height Bits [9:0]
These bits specify the LCD panel and/or the CRT vertical display height, in 1-line resolution. For a
dual LCD panel only configuration, this register should be programmed to half the panel size.
Vertical display height in number of lines = (ContentsOfThisRegister) + 1.
The maximum vertical display height is 1024 lines.
HRTC/ HRTC/
FPLINE Pulse FPLINE Pulse
Width Bit 3 Width Bit 2
active high
active low
Vertical Vertical
Display Display
Height Bit 3 Height Bit 2
n/a n/a
HRTC/ HRTC/
FPLINE Pulse FPLINE Pulse
Width Bit 1 Width Bit 0
TFT FPLINE Polarity
active low
active high
Vertical Vertical
Display Display
Height Bit 1 Height Bit 0
Vertical Vertical
Display Display
Height Bit 9 Height Bit 8
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S1D13504
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