Mcf5307 To S1D13504 Interface; Hardware Connections - Epson S1D13504 Technical Manual

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4 MCF5307 To S1D13504 Interface

When connecting the S1D13504 RESET# pin, the system designer should be aware of all

conditions that may reset the S1D13504 (e.g. CPU reset can be asserted during wake-up

from power-down modes, or during debug states).

Figure 4-1: Typical Implementation of MCF5307 to S1D13504 Interface

Interfacing to the Motorola MCF5307 "Coldfire" Microprocessor

Issue Date: 01/02/02

The interface between the S1D13504 and the MCF5307 requires minimal glue logic. Since

the S1D13504 has a single chip select input for both display RAM and registers, a single

external gate is required to produce a negative-OR function of the two MCF5307 chip

selects. A single resistor is used to speed up the rise time of the WAIT# (TA) signal when

terminating the bus cycle.

BS# (bus start) is not used in this implementation and should be tied low (connected GND).

The following diagram shows a typical implementation of the MCF5307 to S1D13504

For pin mapping see Table 3-1:, "Generic MPU Host Bus Interface Pin Mapping" .

74AC08 (or equiv.)

System RESET

X19A-G-011-07

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