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7.1.5 Generic MPU Interface Asynchronous Timing
T
BCLK
BCLK
A[20:0]
M/R#
CS#
t2
RD0#,RD1#
WE0#,WE1#
Hi-Z
WAIT#
Hi-Z
D[15:0](write)
Hi-Z
D[15:0](read)
S1D13504
X19A-A-002-19
Valid
t1
t4
t6
t8
Figure 7-5: Generic MPU Interface Asynchronous Timing
Epson Research and Development
Valid
t9
Valid
Hardware Functional Specification
Vancouver Design Center
t3
t5
Hi-Z
t7
Hi-Z
t10
Hi-Z
Issue Date: 01/11/06