Registers - Epson S1D13504 Technical Manual

Page 26

4.2.1 Registers

REG[10h] Screen 1 Display Start Address 0
Start Address Start Address
Bit 7 Bit 6
REG[11h] Screen 1 Display Start Address 1
Start Address Start Address
Bit 15 Bit 14
REG[12h] Screen 1 Display Start Address 2
n/a n/a
REG[18h] Pixel Panning Register
Screen 2 Screen 2
Pixel Pan Pixel Pan
Bit 3 Bit 2
S1D13504
X19A-G-002-07
Start Address Start Address
Bit 5 Bit 4
Start Address Start Address
Bit 13 Bit 12
n/a
These three registers form the address of the word in the display buffer where screen 1 will start
displaying from. Changing these registers by one will cause a change of 0 to 16 pixels depending on
the current color depth. Refer to the following table to see the minimum number of pixels affected
by a change of one to these registers.
Table 4-1: Number of Pixels Panned Using Start Address
Color Depth (bpp) Pixels per Word
1
2
4
8
15
16
Screen 2 Screen 2
Pixel Pan Pixel Pan
Bit 1 Bit 0
The pixel panning register offers finer control over pixel pans than is available with the Start Address
Registers. Using this register it is possible to pan the displayed image one pixel at a time. Depending
on the current color depth certain bits of the pixel pan register are not used. The following table
shows this.
Table 4-2: Active Pixel Pan Bits
Color Depth (bpp)
1
2
4
8
15/16
Start Address Start Address
Bit 3
Start Address Start Address
Bit 11
Start Address Start Address
n/a
Bit 19
Number of Pixels Panned
16
8
4
2
1
1
Screen 1 Screen 1
Pixel Pan Pixel Pan
Bit 3 Bit 2
Pixel Pan bits used
bits [3:0]
bits [2:0]
bits [1:0]
bit 0
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Epson Research and Development
Vancouver Design Center
Start Address
Bit 2 Bit 1
Start Address
Bit 10 Bit 9
Start Address
Bit 18 Bit 17
16
8
4
2
1
1
Screen 1
Pixel Pan
Bit 1
Programming Notes and Examples
Issue Date: 01/02/01
Start Address
Bit 0
Start Address
Bit 8
Start Address
Bit 16
Screen 1
Pixel Pan
Bit 0