Mpc821 To S1D13504 Interface; Hardware Description - Epson S1D13504 Technical Manual

Color graphics lcd/crt controller

Hide thumbs Also See for S1D13504:

Table of Contents

Epson Research and Development

Vancouver Design Center

4 MPC821 to S1D13504 Interface

When connecting the S1D13504 RESET# pin, the system designer should be aware of all

conditions that may reset the S1D13504 (e.g. CPU reset can be asserted during wake-up

from power-down modes, or during debug states).

Figure 4-1: Typical Implementation of MPC821 to S1D13504 Interface

Interfacing to the Motorola MPC821 Microprocessor

Issue Date: 01/10/26

The interface between the S1D13504 and the MPC821 requires no glue logic. All lines are

directly connected. A single resistor is used to speed up the rise time of the WAIT# (TA)

signal when terminating the bus cycle.

BS# (bus start) is not used in this implementation and must be connected to IO V

The following diagram shows a typical implementation of the MPC821 to S1D13504

For pin mapping see Table 3-1:, "Generic MPU Host Bus Interface Pin Mapping" .

System RESET

X19A-G-010-06

Table of Contents