Epson S1D13504 Technical Manual page 424

Color graphics lcd/crt controller

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X19A-G-005-09

The Generic MPU host interface control signals of the S1D13504 are asynchronous with

respect to the S1D13504 bus clock. This gives the system designer full flexibility in

choosing the appropriate source (or sources) for CLKI and BUSCLK. Deciding whether

both clocks should be the same and whether to use DCLKOUT (divided) as the clock

source, should be based on the desired:

• pixel and frame rates.

• power budget.

• part count.

• maximum S1D13504 clock frequencies.

The S1D13504 also has internal clock dividers providing additional flexibility.

Epson Research and Development

Interfacing to the Philips MIPS PR31500/PR31700 Processor

Vancouver Design Center

Issue Date: 01/10/26

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