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Table 3-1: Configuration DIP Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 3-2: Jumper Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 4-1: CPU Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 4-2: CPU/BUS Connector (H1) Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 4-3: CPU/BUS Connector (H2) Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 4-4: LCD Signal Connector (J1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 4-5: Controlling the MAX754 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 4-6: Controlling the MAX749 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 6-1: Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 3-1: Configuration DIP Switch (S1) Location . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 3-2: Configuration Jumper (JP1) Location . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 3-3: Configuration Jumper (JP2) Location . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 3-4: Configuration Jumper (JP3) Location . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 3-5: Configuration Jumper (JP4) Location . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 3-6: Configuration Jumper (JP5) Location . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 3-7: Configuration Jumper (JP6) Location . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 3-8: Configuration Jumper (JP7) Location . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 7-1: S5U13504B00C Rev. 2.0 Evaluation Board Schematics (1 of 5) . . . . . . . . . . . . . 25
Figure 7-2: S5U13504B00C Rev. 2.0 Evaluation Board Schematics (2 of 5) . . . . . . . . . . . . . 26
Figure 7-3: S5U13504B00C Rev. 2.0 Evaluation Board Schematics (3 of 5) . . . . . . . . . . . . . 27
Figure 7-4: S5U13504B00C Rev. 2.0 Evaluation Board Schematics (4 of 5) . . . . . . . . . . . . . 28
Figure 7-5: S5U13504B00C Rev. 2.0 Evaluation Board Schematics (5 of 5) . . . . . . . . . . . . . 29
Figure 8-1: S5U13504B00C Rev. 2.0 Evaluation Board Layout . . . . . . . . . . . . . . . . . . . . 30
S5U13504B00C Rev. 2.0 PCI Evaluation Board User Manual
Issue Date: 2002/12/02
List of Tables
List of Figures
Page 5
S1D13504
X19A-G-014-01
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