Epson Research and Development
Vancouver Design Center
FPFRAME
FPLINE
FPLINE
DRDY
t1
t2
t3
FPSHIFT
R[5:1]
G[5:0]
B[5:1]
Note: DRDY is used to indicate the first pixel
Hardware Functional Specification
Issue Date: 01/11/06
t9
t12
t7
t17
t11
Figure 7-38: TFT A.C. Timing
t8
t6
t14
t13
t4
t5
1
2
639
t10
Page 83
t15
t16
640
S1D13504
X19A-A-002-19