Vancouver Design Center - Epson S1D13504 Technical Manual

Epson Research and Development

Vancouver Design Center

Pin Name Type
F00A
F01A
43, 41,
39, 37,
MA[8:0] O 35, 34,
36, 38,
40
MA9 IO 45
MA10 IO 42
MA11 IO 44
1 When configured as IO pins.
Hardware Functional Specification
Issue Date: 01/11/06
Table 5-2: Memory Interface Pin Descriptions (Continued)
Pin #
Reset = 0
Driver
Value
F02A
46, 44,
42, 40,
41, 43, CO1 Output 0
45, 47,
49
Hi-Z /
51 C/TS1
Output 0
Hi-Z /
48 C/TS1
Output 0
Hi-Z /
50 C/TS1
Output 0
Multiplexed memory address.
This pin has multiple functions.
• For 2M byte DRAM, this is memory address bit 9 (MA9).
• For asymmetrical 512K byte DRAM, this is memory address
bit 9 (MA9).
1
• For symmetrical 512K byte DRAM, this pin can be used as
general purpose IO (GPIO3).
See Table 5-10: "Memory Interface Pin Mapping," on page 32
for summary.
This pin has multiple functions.
• For asymmetrical 2M byte DRAM, this is memory address bit
10 (MA10).
• For symmetrical 2M byte DRAM and all 512K byte DRAM,
1
this pin can be used as general purpose IO (GPIO1).
See Table 5-10: "Memory Interface Pin Mapping," on page 32
for summary.
This pin has multiple functions.
• For asymmetrical 2M byte DRAM, this is memory address bit
11 (MA11).
• For symmetrical 2M byte DRAM and all 512K byte DRAM,
1
this pin can be used as general purpose IO (GPIO2).
See Table 5-10: "Memory Interface Pin Mapping," on page 32
for summary.
Description
X19A-A-002-19
Page 25
S1D13504