S1D13504 Host Bus Interface; Generic Mpu Host Bus Interface Pin Mapping - Epson S1D13504 Technical Manual

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3 S1D13504 Host Bus Interface

3.1 Generic MPU Host Bus Interface Pin Mapping

Interfacing to the Toshiba MIPS TX3912 Processor
Issue Date: 01/10/26
The S1D13504 implements a 16-bit Generic MPU host bus interface which is used to
interface to the Toshiba TX3912 processor. The Generic MPU host bus interface is the least
processor-specific interface mode supported by the S1D13504 and was chosen to
implement this interface due to the simplicity of its timing.
The Generic MPU host bus interface is selected by the S1D13504 on the rising edge of
RESET#. After releasing reset the bus interface signals assume their selected configuration.
Note
After reset, the Host Interface Disable bit in the Miscellaneous Disable Register
(REG[1Bh]) will be set to logic '1', meaning that the S1D13504 will not respond to any
host accesses until a write to REG[1Bh] clears this bit to 0. When debugging a new
hardware design, this can sometimes give the appearance that the interface is not work-
ing, so it is important to remember to clear this bit before proceeding with debugging.
The following table shows the functions of each host bus interface signal.
Table 3-1: Generic MPU Host Bus Interface Pin Mapping
S1D13504
Pin Names
AB[20:1]
AB0
DB[15:0]
WE1#
M/R#
CS#
BUSCLK
BS#
RD/WR#
RD#
WE0#
WAIT#
RESET#
Generic MPU
A[20:1]
A0
D[15:0]
WE1#
External Decode
External Decode
BCLK
Connect to IO V
DD
RD1#
RD0#
WE0#
WAIT#
RESET#
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