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Page 108
bit 4
REG[22h] Bit 4
bits 3-2
REG[22h] Bits [3:2]
S1D13504
X19A-A-002-19
RAS# to CAS# Delay (N
RCD
This bit selects the DRAM RAS# to CAS# delay parameter, t
(N
) of MCLK periods (T
RCD
access time, t
. Note, these formulae assume an MCLK duty cycle of 50 +/- 5%.
RAC
N
= Round-Up((t
RCD
RAC
= 2
= Round-Up(t
RAC
= Round-Up(t
RAC
Note that for EDO-DRAM and N
N
. This is done to satisfy the CAS# address setup time, t
RCD
The resulting t
is related to N
RC
t
= (N
) T
RC
RCD
t
= (1.5) T
RC
M
t
= (N
+ 0.5) T
RC
RCD
t
= (N
) T
RC
RCD
Table 8-12: RAS-to-CAS Delay Timing Select
0
1
RAS# Precharge Timing (N
Minimum Memory Timing for RAS precharge
These bits select the DRAM RAS# Precharge timing parameter, t
(N
) of MCLK periods (T
RP
assume an MCLK duty cycle of 50 +/- 5%.
N
= 1
RP
= 1.5
= 2
The resulting t
is related to N
RC
t
= (N
+ 0.5) T
RC
RP
t
= (N
) T
RC
RP
M
Table 8-13: RAS Precharge Timing Select
00
01
10
11
)
) used to create t
. N
M
RCD
+ 5)/T
- 1)
if EDO and N
M
if EDO and N
/T
- 1)
if FPM and N
M
/T
- 0.45)
if FPM and N
M
= 1.5, this bit is automatically forced to 0 to select 2 MCLK for
RP
as follows:
RCD
if EDO and N
M
RP
if EDO and N
RP
if FPM and N
M
RP
if FPM and N
M
RP
N
RCD
2
1
) Bits [1:0]
RP
) used to create t
- see the following formulae. Note, these formulae
M
RP
if (t
/T
) < 1
RP
M
if 1 ≤ (t
/T
) < 1.45
RP
M
) ≥ 1.45
if (t
/T
RP
M
as follows:
RP
if FPM refresh cycle and N
M
for all other
N
RP
2
1.5
1
Reserved
Epson Research and Development
Vancouver Design Center
. This bit specifies the number
RCD
must be chosen to satisfy the RAS#
RCD
= 1 or 2
RP
= 1.5
RP
= 1 or 2
RP
= 1.5
RP
.
ASC
= 1 or 2
= 1.5
= 1 or 2
= 1.5
RAS# to CAS# Delay (t
RCD
2 T
M
1 T
M
. These bits specify the number
RP
= 1 or 2
RP
RAS# Precharge Width (t
RP
2 T
M
1.5 T
M
1 T
M
Reserved
Hardware Functional Specification
Issue Date: 01/11/06
)
)
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