Table 7-8: Edo Dram Write Timing; Vancouver Design Center - Epson S1D13504 Technical Manual

Epson Research and Development

Vancouver Design Center

Symbol
t1
Memory clock period
Random read or write cycle time (REG[22h] bits [6:5] = 00)
t2 Random read or write cycle time (REG[22h] bits [6:5] = 01)
Random read or write cycle time (REG[22h] bits [6:5] = 10)
Row address setup time (REG[22h] bits [3:2] = 00)
t3 Row address setup time (REG[22h] bits [3:2] = 01)
Row address setup time (REG[22h] bits [3:2] = 10)
Row address hold time (REG[22h] bits [3:2] = 00 or 10)
t4
Row address hold time (REG[22h] bits [3:2] = 01)
t5
Column address setup time
t6
Column address hold time
t7
CAS# pulse width
t8
CAS# precharge time
t9
RAS# hold time
RAS# precharge time (REG[22h] bits [3:2] = 00)
t10 RAS# precharge time (REG[22h] bits [3:2] = 01)
RAS# precharge time (REG[22h] bits [3:2] = 10)
RAS# to CAS# delay time
(REG[22h] bit 4 = 0 and bits [3:2] = 00 or 10)
t11 RAS# to CAS# delay time
(REG[22h] bit 4 = 1 and bits [3:2] = 00 or 10)
RAS# to CAS# delay time (REG[22h] bits [3:2] = 01)
t12
Write command setup time
t13
Write command hold time
t14
Write Data setup time
t15
Write Data hold time
Hardware Functional Specification
Issue Date: 01/11/06

Table 7-8: EDO DRAM Write Timing

Parameter Min Typ Max
25
5 t1
4 t1
3 t1
2.45 t1
2 t1
1.45 t1
0.45 t1 - 1
t1 - 1
0.45 t1 - 1
0.45 t1 - 1
0.45 t1 0.55 t1 + 1
0.45 t1 - 1 0.55 t1
1 t1
2 t1 - 1
1.45 t1 - 1
1 t1 - 1
2 t1 - 2 2 t1
1 t1 - 2 1 t1
1.45 t1 - 2 1.55 t1
0.45 t1 - 1
0.45 t1
0.45 t1 - 3
0.45 t1 - 2
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S1D13504
X19A-A-002-19