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Page 26
5.4.3 LCD Interface
Pin Name
Type
FPDAT[8:0]
O
88, 82-75 98, 92-85 CN3
FPDAT[15:9] O
95-89
FPFRAME
O
69
FPLINE
O
70
FPSHIFT
O
73
LCDPWR
O
71
DRDY
O
72
1
Output may be 1 or 0.
5.4.4 Clock Input
Pin Name
Type
F00A
F01A
CLKI
I
105
S1D13504
X19A-A-002-19
Table 5-3: LCD
Pin #
Driver
F00A
F02A
F!A
105-99
CN3
79
CN3
80
CN3
83
CN3
81
CO1
82
CN3
Table 5-4: Clock Input
Pin #
Driver
F02A
119
C
Interface Pin Descriptions
Reset =
0 Value
Output 0 Panel Data
These pins have multiple functions.
• Panel Data for 16-bit panels.
Output 0
• Pixel Data for external RAMDAC support.
See Table 5-11: "LCD, CRT, RAMDAC Interface Pin
Mapping," on page 33.
Output 0 Frame Pulse
Output 0 Line Pulse
Output 0 Shift Clock Pulse
LCD power control output. The active polarity of this output
is selected by the state of MD10 at the rising edge of
RESET# - see Section 5.5, "Summary of Configuration
Options" on page 30.
1
Output
This output is controlled by the power save mode circuitry -
see Section 13, "Power Save Modes" on page 127 for
details.
This pin has multiple functions which are automatically
selected depending on panel type used.
• For TFT panels, this is the display enable output
(DRDY).
• For passive LCDs with Format 1 interfaces, this is the
Output 0
2nd Shift Clock (FPSHIFT2).
• For all other LCD panels, this is the LCD backplane bias
signal (MOD).
See Table 5-11: "LCD, CRT, RAMDAC Interface Pin
Mapping," on page 33 and REG[02h] for details.
Pin Description
Reset =
0 Value
Input clock for the internal pixel clock (PCLK) and memory
Hi-Z
clock (MCLK). PCLK and MCLK are derived from CLKI – see
REG[19h] for details.
Epson Research and Development
Vancouver Design Center
Description
Description
Hardware Functional Specification
Issue Date: 01/11/06
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