Lcd Memory Access Cycles - Epson S1D13504 Technical Manual

Epson Research and Development
Vancouver Design Center

2.1.2 LCD Memory Access Cycles

TCLK
ADD[25:0]
SHB#
LCDCS#
WR#,RD#
D[15:0]
(write)
D[15:0]
(read)
LCDRDY
Interfacing to the NEC VR4102™ Microprocessor
Issue Date: 01/10/26
Once an address in the LCD block of memory is placed on the external address bus
(ADD[25:0]), the LCD chip select (LCDCS#) is driven low. The read or write enable
signals (RD# or WR#) are driven low for the appropriate cycle and LCDRDY is driven low
to insert wait states into the cycle. The high byte enable (SHB#) is driven low for 16-bit
transfers and high for 8-bit transfers.
The following figure illustrates typical NEC VR4102 memory read and write cycles to the
LCD controller interface.
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Figure 2-1: NEC VR4102 Read/Write Cycles
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S1D13504
X19A-G-007-08