Table 7-5: Generic Mpu Interface Asynchronous Timing; Vancouver Design Center - Epson S1D13504 Technical Manual

Epson Research and Development

Vancouver Design Center

Symbol
T
Bus clock period
BCLK
t1
RD0#, RD1#, WE0#, WE1# low to CS# low
t2
A[20:0], M/R# valid to RD0#, RD1#, WE0#, WE1# low
t3
RD0#, RD1#, WE0#, WE1# high to A[20:0], CS#, M/R# invalid and CS# high
1
t4
CS# low to WAIT# driven low
t5
RD0#, RD1#, WE0#, WE1# high to WAIT# high impedance
t6
WE0#, WE1# low to D[15:0] valid (write cycle)
t7
D[15:0] hold from WE0#, WE1# high (write cycle)
2
t8
RD0#, RD1# low to D[15:0] driven (read cycle)
t9
D[15:0] valid to WAIT# high (read cycle)
t10
RD0#, RD1# high to D[15:0] high impedance (read cycle)
Hardware Functional Specification
Issue Date: 01/11/06

Table 7-5: Generic MPU Interface Asynchronous Timing

Parameter
1. If the S1D13504 host interface is disabled, the timing for WAIT# driven low is relative to the
falling edge of CS# or the first positive edge of BCLK after A[20:0] and M/R# become valid,
whichever occurs later.
2. If the S1D13504 host interface is disabled, the timing for D[15:0] driven is relative to the fall-
ing edge of RD0#, RD1# or the first positive edge of BCLK after A[20:0] and M/R# become
valid,
whichever occurs later.
Page 45
Min Max Units
25 ns
4 ns
0 ns
0 ns
1 7 ns
1 6 ns
20 ns
0 ns
3 15 ns
0
2 10
S1D13504
X19A-A-002-19