S1D13504 Host Bus Interface; Generic Mpu Host Bus Interface Pin Mapping - Epson S1D13504 Technical Manual

Color graphics lcd/crt controller

Hide thumbs Also See for S1D13504:

Table of Contents

Epson Research and Development

Vancouver Design Center

3 S1D13504 Host Bus Interface

Interfacing to the Motorola MC68328 "Dragonball" Microprocessor

Issue Date: 01/10/26

This section is summary of the bus interface modes available on the S1D13504, and offers

some detail on the Generic MPU host bus interface used to implement the interface to the

The Generic MPU host bus interface is selected by the S1D13504 on the rising edge of

RESET#. After releasing reset the bus interface signals assume their selected configuration.

After reset, the Host Interface Disable bit in the Miscellaneous Disable Register

(REG[1Bh]) will be set to logic '1', meaning that the S1D13504 will not respond to any

host accesses until a write to REG[1Bh] clears this bit to 0. When debugging a new

hardware design, this can sometimes give the appearance that the interface is not work-

ing, so it is important to remember to clear this bit before proceeding with debugging.

The following table shows the functions of each host bus interface signal.

Table 3-1: Generic MPU Host Bus Interface Pin Mapping

External Decode

Connect to IO V

X19A-G-013-03

Table of Contents