Single Color 4-Bit Panel Timing; Figure 7-23: Single Color 4-Bit Panel Timing - Epson S1D13504 Technical Manual

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7.4.5 Single Color 4-Bit Panel Timing

FPFRAME
FPLINE
MOD
UD[3:0]
FPLINE
MOD
FPSHIFT
UD3
UD2
UD1
UD0
* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 640x480 panel
VDP
= Vertical Display Period
VNDP
= Vertical Non-Display Period
HDP
= Horizontal Display Period
HNDP
= Horizontal Non-Display Period
S1D13504
X19A-A-002-19
VDP
LINE1
LINE2
LINE3
LINE4
HDP
1-R1
1-G2
1-B3
1-G1
1-B2
1-R4
1-B1
1-R3
1-G4
1-R2
1-G3
1-B4

Figure 7-23: Single Color 4-Bit Panel Timing

= (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1
= (REG[0Ah] bits [5:0]) + 1
= ((REG[04h] bits [6:0]) + 1)*8Ts
= ((REG[05h] bits [4:0]) + 1)*8Ts
Epson Research and Development
VNDP
LINE479 LINE480
1-B319
1-R320
1-G320
1-B320
Hardware Functional Specification
Vancouver Design Center
LINE1
LINE2
HNDP
Issue Date: 01/11/06

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